2015/16 Undergraduate Module Catalogue

COMP1212 Computer Processors

10 creditsClass Size: 130

Module manager: Dr Kevin McEvoy
Email: K.McEvoy@leeds.ac.uk

Taught: Semester 1 (Sep to Jan) View Timetable

Year running 2015/16

This module is not approved as a discovery module

Module summary

Effective programming depends on understanding not only how to give a machine instructions (the software), but also on how the machine carries out those instructions (the hardware). Modern hardware is built up in layers upon simple structures, and this module will introduce the student to how a computer chip actually computes, how data is represented in memory, and how simple electronic circuits are built up to provide complex logic.

Objectives

On completion of this module, students should be able to:
-Describe a computer, program or network protocol as a state machine.
-Develop state machine descriptions for simple problem statement solutions
-Describe the basic building blocks of computers and their role in the historical development of computer architecture.
-Design a simple logic circuit using the fundamental building blocks of logic design.
-Use tools for capture, synthesis, and simulation to evaluate a logic design.
-Describe the progression of computer technology components from vacuum tubes to VLSI, from mainframe computer architectures to the organization of warehouse-scale computers.
-Comprehend the trend of modern computer architectures towards multi-core and that parallelism is inherent in all hardware systems.
-Design the basic building blocks of a computer: arithmetic-logic unit (gate-level), registers (gate-level), central processing unit (register transfer-level), memory (register transfer-level).
-Use CAD tools for capture, synthesis, and simulation to evaluate simple building blocks (e.g., arithmetic logic unit, registers, movement between registers) of a simple computer design.
-Identify the main types of memory technology (e.g., SRAM, DRAM, Flash, magnetic disk) and their relative cost and performance.
-Calculate average memory access time and describe the tradeoffs in memory hierarchy performance in terms of capacity, miss/hit rate, and access time.

Learning outcomes
On completion of the year/programme students should have provided evidence of being able to:
- demonstrate a familiarity with the basic concepts, information, practical competencies and techniques which are standard features of the discipline;
- be able to communicate the results of their work;
- be able to interpret and evaluate the underlying concepts and principles of the discipline;
- evaluate qualitative and/or quantitative data;
- appreciate their strengths and weaknesses as learners;
- demonstrate an awareness of professional and disciplinary boundaries;
- demonstrate computational thinking including its relevance to everyday life;
- operate computing equipment effectively, taking into account its logical and physical properties.

Syllabus

State & State Machines:
Digital vs. Analog/Discrete vs. Continuous Systems; Simple logic gates, logical expressions, Boolean logic simplification; Clocks, State, Sequencing; Combinational Logic, Sequential Logic, Registers, Memories; Computers and Network Protocols as examples of state machines

Computational Paradigms:
Basic building blocks and components of a computer (gates, flip-flops, registers, interconnections; Datapath + Control + Memory); Hardware as a computational paradigm: Fundamental logic building blocks; Logic expressions, minimization, sum of product forms; Basic concept of pipelining, overlapped processing stages; Basic concept of scaling: going faster vs. handling larger problems

Digital Logic and Digital Systems:
Overview and history of computer architecture; Combinational vs. sequential logic/Field programmable gate arrays as a fundamental combinational + sequential logic building block; Multiple representations/layers of interpretation (hardware is just another layer); Computer-aided design tools that process hardware and architectural representations; Register transfer notation/Hardware Description Language (Verilog/VHDL); Physical constraints (gate delays, fan-in, fan-out, energy/power)

Memory System Organisation & Architecture:
Storage systems and their technology; Memory hierarchy: importance of temporal and spatial locality; Main memory organization and operations; Latency, cycle time, bandwidth, and interleaving; Cache memories (address mapping, block size, replacement and store policy); Multiprocessor cache consistency/Using the memory system for inter-core synchronization/atomic memory operations; Virtual memory (page table, TLB); Fault handling and reliability; Error coding, data compression, and data integrity.

Evaluation:
CPI (Cycles per Instruction) equation as tool for understanding tradeoffs in the design of instruction sets, processor pipelines, and memory system organizations. Amdahl’s Law: the part of the computation that cannot be sped up limits the effect of the parts that can.
Proximity:
Speed of light and computers (one foot per nanosecond vs. one GHz clocks). Latencies in computer systems: memory vs. disk latencies vs. across the network memory. Caches and the effects of spatial and temporal locality on performance in processors and systems. Caches and cache coherency in databases, operating systems, distributed systems, and computer architecture. Introduction into the processor memory hierarchy and the formula for average memory access time.

Teaching methods

Delivery type	Number	Length hours	Student hours
Example Class	5	1.00	5.00
Laboratory	5	1.00	5.00
Class tests, exams and assessment	1	2.00	2.00
Lecture	22	1.00	22.00
Private study hours			66.00
Total Contact hours			34.00
Total hours (100hr per 10 credits)			100.00

Opportunities for Formative Feedback

Coursework and labs.

Methods of assessment

Coursework

Assessment type	Notes	% of formal assessment
Problem Sheet	Problem Sheet 1	15.00
Problem Sheet	Problem Sheet 2	15.00
Total percentage (Assessment Coursework)		30.00

This module is re-assessed by exam only.

Exams

Exam type	Exam duration	% of formal assessment
Open Book exam	2 hr	70.00
Total percentage (Assessment Exams)		70.00

This module is re-assessed by exam only.

Reading list

There is no reading list for this module

Last updated: 05/11/2015

Disclaimer

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