2016/17 Taught Postgraduate Module Catalogue

ELEC5566M FPGA Design for System-on-Chip

15 creditsClass Size: 75

Module manager: Dr Steven Freear
Email: s.freear@leeds.ac.uk

Taught: Semester 2 (Jan to Jun) View Timetable

Year running 2016/17

Pre-requisite qualifications

Students are required to have at least ONE of the following pre-requisites: ELEC3662 or ELEC5681M or ELEC5685M

This module is not approved as an Elective

Objectives

On completion of this module students will:
1. Utilize hardware description language (Verilog and System Verilog) to design FPGA based digital systems;
2. understand the principles of the design of System on Chip systems for FPGA technologies;
3. have a detailed knowledge of scalable design leading to intellectual property (IP) design blocks;
4. understand the fundamentals of implementing complex systems on a single chip (System-on-Chip);
5. develop self checking test benches for verification of IP blocks;
6. be able to use contemporary EDA design tools to design practical examples with hardware verification using Terasic DE1-SoC FPGA platforms.

Syllabus

1. The principles of the design of a FPGA systems using Hardware Description Language (Verilog).
2. The use of contemporary EDA design tools: Altera Quartus.
3. Test bench for digital design verification using Mentor Graphics ModelSim
4. Design of sequential systems using finite state machines.
5. Using fixed point numbering systems to design arithmetic signal processing blocks.
6. Use of bus systems for interlinking complex IP blocks.
7. Parameterisation and re-use for the generation of IP blocks.

Teaching methods

Delivery type	Number	Length hours	Student hours
Class tests, exams and assessment	1	3.00	3.00
Lecture	10	0.50	5.00
Practical	10	3.00	30.00
Independent online learning hours			30.00
Private study hours			82.00
Total Contact hours			38.00
Total hours (100hr per 10 credits)			150.00

Private study

Students are expected to read extensively in order to understand and complete the mini projects and the main project. The project will be partly carried out in timetabled classes and partly in the students' own time.

Opportunities for Formative Feedback

Students' progress is monitored by assignments and an in-class programming assessment upon which feedback is given.

Methods of assessment

Coursework

Assessment type	Notes	% of formal assessment
Assignment	Assignment 1	10.00
Assignment	Assignment 2	20.00
Computer Exercise	In-class programming assessment	20.00
Project	Technical Report	25.00
Project	Oral viva	25.00
Total percentage (Assessment Coursework)		100.00

Normally resits will be assessed by the same methodology as the first attempt, unless otherwise stated

Reading list

There is no reading list for this module

Last updated: 27/02/2017

Disclaimer

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