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2012/13 Taught Postgraduate Module Catalogue

ELEC5610M Embedded Systems Design

15 creditsClass Size: 80

Module manager: Dr L Mhamdi
Email: l.mhamdi@leeds.ac.uk

Taught: Semester 2 (Jan to Jun) View Timetable

Year running 2012/13

Pre-requisite qualifications

Standard degree entry / progression criteria

This module is not approved as an Elective

Objectives

The module provides students with a knowledge and understanding of embedded systems and their applications to communications/networking systems design. The first part of the module covers topics on embedded systems design, key components (i.e., hardware, software and firmware), trade-offs between software and firmware implementations, the design process, etc. The second part of the module deals with networking systems design as an example of embedded systems. It covers topics on the design, analysis and performance evaluation of a wide range of network architectures with a special emphasis on high-performance switches and Internet routers. Students will learn the architectural evolution of routers and switches, analyse their performance and hardware cost, gain insights to their limitations, etc. In particular, the course provides a basis for understanding, appreciating and performing practical research and development in embedded systems and networking infrastructure, switches and routers.

Learning outcomes
- Understand the architecture and organisation of embedded systems (hardware, software, firmware)
- Understand the top level design process
- Understand the trade-offs between software and firmware implementations of algorithms
- Understand the architecture, operation and evolution of network infrastructure, switches and routers.
- Design and analyse various switching architectures using software tools (simulation) and hardware tools (FPGA).
- Evaluate the performance (both system level and hardware level) and cost of key interconnection components.
- Build learning and research skills (survey, research methodologies & conclusion) through project investigation.

Syllabus

- Introduction to embedded systems.
- Discussion of the key elements of an embedded system: hardware (ARM and FPGAs), software and/or firmware.
- Interfacing to the ‘real world’– analogy with ADCs and DACs.
- Trade-offs between software implementation and firmware implementation.
- The design process – requirements specification, test specification and the close.
- Discussion of actual systems implemented: communications systems.
- Overview: evolution of interconnection networks and internetworking, evolution of packet switches and routers, basic architectural components and architectures, some example architectures.
- High-performance packet switches/routers: architectural alternatives, the Virtual Output Queued (VOQ) switching architecture; design and analysis of VOQ schedulers, the scheduling problem and optimal scheduling; design of practical schedulers, Parallel Iterative Matching and alternative algorithms design.
- Performance analysis: system level performance of Internet routers and switches using software tools (simulation), prototyping example key interconnection components using hardware tools (FPGA).
- Providing performance guarantees in Internet routers and switches: ideal architecture, output queuing (OQ) & shared memory switches, emulating an ideal router and providing QoS.

Teaching methods

Delivery type	Number	Length hours	Student hours
Lecture	10	2.00	20.00
Practical	1	2.00	2.00
Private study hours			128.00
Total Contact hours			22.00
Total hours (100hr per 10 credits)			150.00

Private study

- Reading lecture notes, textbook(s) and directed reading (research papers);
- Working on course project
- Write-up of project report
- Preparing presentation.

Opportunities for Formative Feedback

Non-timetabled meetings to discuss project work; project presentations

Methods of assessment

Coursework

Assessment type	Notes	% of formal assessment
Report	Report & Final Presentation	50.00
Total percentage (Assessment Coursework)		50.00

Normally resits will be assessed by the same methodology as the first attempt, unless otherwise stated

Exams

Exam type	Exam duration	% of formal assessment
Standard exam (closed essays, MCQs etc)	3 hr 00 mins	50.00
Total percentage (Assessment Exams)		50.00

Normally resits will be assessed by the same methodology as the first attempt, unless otherwise stated

Reading list

There is no reading list for this module

Last updated: 20/05/2013

Disclaimer

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