2016/17 Taught Postgraduate Module Catalogue
ELEC5461M High Speed Internet Architecture
15 creditsClass Size: 40
Module manager: Dr Lotfi Mhamdi
Email: l.mhamdi@leeds.ac.uk
Taught: Semester 2 (Jan to Jun) View Timetable
Year running 2016/17
This module is not approved as an Elective
Objectives
High performance routers are needed to support the development and delivery of advanced network services over high-speed Internet. Routers and switches are the key building blocks of the Internet, and consequently, the capability of the Internet in all its aspects depends on the capability of its switches and routers. The goal of this module is to provide a basis for understanding, appreciating, and performing practical research and development in networking with a special emphasis on Internet routers and switches. It covers topics on the design, analysis and performance evaluation of a wide range of network architectures, switches and Internet routers. Students will learn the architectural evolution of routers and switches, analyse their performance and hardware cost and gain insights to their limitations.Learning outcomes
On completion of this module, students should be able to ...
- Understand the architecture, operation and evolution of the Internet infrastructure, switches and routers.
- Design and analyse various switching architectures at the software level as well as the hardware level.
- Gain insights to the advantages and limitations of existing Internet routers and switches architectures
- Evaluate the performance (both system level and hardware level) and cost of various routers architectures and interconnection components.
- Build learning and research skills (survey, research methodologies & conclusion) through project investigation.
Syllabus
Survey of the state of the art in High-performance Internet routers and switches; Issues involved in designing switches and routers and their architectural trade-offs including protocols, architectures, algorithms, and performance evaluation; Routers' architectures including single and multi-stage switches, input-queued switches, combined input and output queuing, shared memory switches etc. and their scheduling algorithms and hardware design; Performance evaluation of these architectures, how they provide performance guarantees, assessing their hardware cost and feasibility; Refer to some commercial products and relate them to what we cover in the module; Survey of Data centres infrastructure.
Teaching methods
| Delivery type | Number | Length hours | Student hours |
| Lecture | 10 | 2.00 | 20.00 |
| Tutorial | 3 | 2.00 | 6.00 |
| Private study hours | 124.00 | ||
| Total Contact hours | 26.00 | ||
| Total hours (100hr per 10 credits) | 150.00 | ||
Methods of assessment
Coursework
| Assessment type | Notes | % of formal assessment |
| Project | Group project report | 30.00 |
| Presentation | Individual presentation | 20.00 |
| Total percentage (Assessment Coursework) | 50.00 | |
Normally resits will be assessed by the same methodology as the first attempt, unless otherwise stated
Exams
| Exam type | Exam duration | % of formal assessment |
| Standard exam (closed essays, MCQs etc) | 3 hr 00 mins | 50.00 |
| Total percentage (Assessment Exams) | 50.00 | |
Normally resits will be assessed by the same methodology as the first attempt, unless otherwise stated
Reading list
The reading list is available from the Library websiteLast updated: 08/09/2016
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- Undergraduate module catalogue
- Taught Postgraduate module catalogue
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- Taught Postgraduate programme catalogue
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