2017/18 Undergraduate Module Catalogue

ELEC2655 Gates to PC

20 creditsClass Size: 60

Module manager: Dr Craig Evans
Email: C.A.Evans@leeds.ac.uk

Taught: Semesters 1 & 2 (Sep to Jun) View Timetable

Year running 2017/18

This module is not approved as a discovery module

Module summary

This module aims to give students a deep insight into how a modern computer system works, from the low-level logic gates to high-level programming languages. This is achieved through a series of laboratory tasks in which the students will develop the building blocks of a general purpose computer, before combining them to create a fully-functioning computer. They will then write software (such as games) to run on this computer. The module is based on 'From NAND to Tetris' (http://www.nand2tetris.org/).

Objectives

The objective of this module is for students to develop a modern computer system from the bottom-up using a hardware description language (HDL) and simulator.

They will develop the hardware and then build an assembler and virtual machine (VM) translator so the computer can run software written in a high-level language.

Learning outcomes
On completion of this module, students should be able to:
- Design elementary logic gates from NAND gates;
- Create an arithmetic logic unit (ALU) from logic gates;
- Build a memory system (flip-flops, registers, RAM);
- Combine the ALU and memory system into a computer platform;
- Understand and use an instruction set to write programs in low-level assembly language;
- Understand how an assembler works;
- Understand the role of a compiler and develop a full-scale compiler;
- Appreciate the design trade-offs and efficiency considerations of operating system (OS) design and implementation.

Syllabus

Overview of the Hardware Description Language (HDL) used in the course; implementing logic gates in HDL.

Combinatorial logic: implementation of a binary adder and simple ALU (Arithmetic-Logic Unit) in HDL.

Sequential logic: flip-flop gates, registers and memory cells; design and implementation of a memory hierarchy in HDL.

Machine language: introduction of an instruction set in both binary and assembly language; composition of low-level assembly programs and running them on a CPU emulator.

Computer architecture: integration of the previous designs into a model computer.

Assembler: basic language translation techniques: parsing, symbol table, macro-assembly.

Virtual machines (VM): the role of virtual machines in modern software architectures, introduction of a typical VM language; stack-based flow-of-control and subroutine call-and-return techniques, implementation of a VM which translates into the previously used assembly language.

High Level Language: introduction to a simple Java-like high-level object-based language ("Jack"); discussing trade-offs related to the language design and implementation.

Compilers: context-free grammars and recursive parsing algorithms; code generation, low-level handling of arrays and objects; building a syntax analyser (tokenizer and parser) and full-scale compiler for the Jack language.

Operating system (O/S): discussion of OS/hardware and OS/software design trade-offs, and time/space efficiency considerations; design and implementation of some classical arithmetic and geometric algorithms and classical mathematical, memory management, string processing, and I/O handling algorithms, needed for completing the OS implementation.

Using Jack to write a simple interactive game and running it on the O/S and computer built throughout the module.

Teaching methods

Delivery type	Number	Length hours	Student hours
Class tests, exams and assessment	4	2.00	8.00
Lecture	7	1.00	7.00
Lecture	22	1.00	22.00
Practical	22	2.00	44.00
Private study hours			119.00
Total Contact hours			81.00
Total hours (100hr per 10 credits)			200.00

Opportunities for Formative Feedback

Student progress and engagement will be monitored through progress in the laboratory sessions and mid-semester test.

Methods of assessment

Coursework

Assessment type	Notes	% of formal assessment
In-course Assessment	Semester 1 mid-semester test	25.00
In-course Assessment	Semester 1 end of semester test	25.00
In-course Assessment	Semester 2 mid-semester test	25.00
In-course Assessment	Semester 2 end of semester test	25.00
Total percentage (Assessment Coursework)		100.00

Re-sits for ELEC modules are subject to the rules in the School’s Code of Practice on Assessment. Students should be aware that, for some modules, a re-sit may only be conducted on an internal basis (with tuition) in the next academic session.

Reading list

There is no reading list for this module

Last updated: 26/04/2017

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