2017/18 Undergraduate Module Catalogue

ELEC3285 Integrated Circuit Design

10 creditsClass Size: 100

Module manager: Dr. Paul Steenson
Email: d.p.steenson@leeds.ac.uk

Taught: Semester 2 (Jan to Jun) View Timetable

Year running 2017/18

This module is not approved as a discovery module

Objectives

To provide students with a knowledge , understanding and limited hands-on experience of VLSI design from a mainly Logic circuit based perspective, but including an introduction to contemporary complex VLSI chips, such as CPLDs and FPGAs, and the associated hierarchical and top-down (HDL) design methodologies leading to increasing complexity.

Learning outcomes
Upon completion students should :
understand the foundations of VLSI design and systems
understand combinational and sequential logic representations and circuit implementation
understand the electrical properties of silicon logic, MOSFET and a gate- and switch-level picture of VLSI
Have an appreciation and understanding of physical design and layout and modularization
Be able to use a gate-level layout and synthesis tool (Microwind or equivalent) to analyse the behaviour for some exemplar building blocks
Have an understanding and appreciation of memory devices and circuits and some architectural and system level design via knowledge of interconnects, data flow and synchronization

Syllabus

Introduction to logic design. CMOS physical structure and relation to IC performance limitations.
Electrical representation of MOSFETs and gate primitives. SPICE, switch-level and gate-level modelling.
Design hierarchy and RTL modelling.
Study of some key building blocks; CAD and evaluation.
Data flow and routing: interconnect, bus, and clock distribution overview.
Memory circuits; devices leading to programmable logic.

Teaching methods

Delivery type	Number	Length hours	Student hours
Example Class	2	2.00	4.00
Lecture	18	1.00	18.00
Practical	5	2.00	10.00
Private study hours			68.00
Total Contact hours			32.00
Total hours (100hr per 10 credits)			100.00

Opportunities for Formative Feedback

Through CAD classes and mini-project

Methods of assessment

Coursework

Assessment type	Notes	% of formal assessment
Assignment	CAD Exercise	20.00
Project	Mini Design Project	20.00
Total percentage (Assessment Coursework)		40.00

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Exams

Exam type	Exam duration	% of formal assessment
Standard exam (closed essays, MCQs etc)	2 hr	60.00
Total percentage (Assessment Exams)		60.00

Re-sits for ELEC modules are subject to the rules in the School’s Code of Practice on Assessment. Students should be aware that, for some modules, a re-sit may only be conducted on an internal basis (with tuition) in the next academic session.

Reading list

There is no reading list for this module

Last updated: 08/05/2017

Disclaimer

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