2019/20 Taught Postgraduate Module Catalogue
ELEC5566M FPGA Design for System-on-Chip
15 creditsClass Size: 100
Module manager: Professor Steven Freear
Email: s.freear@leeds.ac.uk
Taught: Semester 2 (Jan to Jun) View Timetable
Year running 2019/20
Pre-requisite qualifications
Students are required to have at least ONE of the following pre-requisites: ELEC3662 or ELEC5681M.This module is not approved as an Elective
Objectives
On completion of this module students will:1. Utilize hardware description language (Verilog HDL) to design FPGA based digital systems;
2. understand the principles of the design of System on Chip systems for FPGA technologies;
3. have a detailed knowledge of scalable design leading to intellectual property (IP) design blocks;
4. understand the fundamentals of implementing complex systems on a single chip (System-on-Chip);
5. develop self checking test benches for verification of IP blocks;
6. be able to use contemporary EDA design tools to design practical examples with hardware verification using Terasic DE1-SoC FPGA platforms.
Syllabus
1. The principles of the design of a FPGA systems using Hardware Description Language (Verilog).
2. The use of contemporary EDA design tools: Altera Quartus.
3. Test bench for digital design verification using Mentor Graphics ModelSim
4. Design of sequential systems using finite state machines.
5. Using fixed point numbering systems to design arithmetic signal processing blocks.
6. Use of bus systems for interlinking complex IP blocks.
7. Parameterisation and re-use for the generation of IP blocks.
Teaching methods
Delivery type | Number | Length hours | Student hours |
Laboratory | 10 | 2.00 | 20.00 |
Class tests, exams and assessment | 1 | 2.00 | 2.00 |
Lecture | 10 | 1.00 | 10.00 |
Independent online learning hours | 30.00 | ||
Private study hours | 88.00 | ||
Total Contact hours | 32.00 | ||
Total hours (100hr per 10 credits) | 150.00 |
Private study
Students are expected to read extensively in order to understand and complete the mini projects and the main project. The project will be partly carried out in timetabled classes and partly in the students' own time.Opportunities for Formative Feedback
Students' progress is monitored by assignments and an in-class programming assessment upon which feedback is given.Methods of assessment
Coursework
Assessment type | Notes | % of formal assessment |
Practical | Programming Test | 30.00 |
Report | Project report | 25.00 |
Assignment | Computer-based assignment | 20.00 |
Viva | Oral examination of project work | 25.00 |
Total percentage (Assessment Coursework) | 100.00 |
Re-sits for ELEC modules are subject to the rules in the School’s Code of Practice on Assessment. Students should be aware that, for some modules, a re-sit may only be conducted on an internal basis (with tuition) in the next academic session.
Reading list
There is no reading list for this moduleLast updated: 30/04/2019
Browse Other Catalogues
- Undergraduate module catalogue
- Taught Postgraduate module catalogue
- Undergraduate programme catalogue
- Taught Postgraduate programme catalogue
Errors, omissions, failed links etc should be notified to the Catalogue Team.PROD