2020/21 Undergraduate Module Catalogue
ELEC3285 Integrated Circuit Design
10 creditsClass Size: 100
Module manager: Dr. Paul Steenson
Email: d.p.steenson@leeds.ac.uk
Taught: Semester 2 (Jan to Jun) View Timetable
Year running 2020/21
This module is not approved as a discovery module
Module summary
The teaching and assessment methods shown below will be kept under review during 2020-21. In particular, if conditions allow for alternative formats of delivery, we may amend the timetable and schedule appropriate classes in addition to (or in place of) the Online Learning Workshops. For Semester 2 (from January 2021), we anticipate that this will be most likely, in which case online teaching will be substituted for traditional face-to-face teaching methods, including lectures and practical classes. ‘Independent online learning’ will involve watching pre-recorded lecture material or screen-casts, engaging in learning activities such as online worked examples or remote/virtual laboratory work, etc. Students will be expected to fully engage with all of these activities. The time commitment for independent online learning, and also the frequency and duration of Online Learning Workshops, are approximate and intended as a guide only. Further details will be confirmed when the module commences.Objectives
To provide students with a knowledge, understanding and hands-on experience of VLSI design from a mainly logic-circuit perspective, but including an introduction to contemporary complex VLSI chips, such as CPLDs and FPGAs, and the associated hierarchical and top-down (HDL) design methodologies leading to increasing complexity.Learning outcomes
On completion of this module students should be able to:
1. Understand the foundations of VLSI design and systems.
2. Understand combinational and sequential logic representations and circuit implementation.
3. Understand the electrical properties of silicon logic, MOSFET and a gate- and switch-level picture of VLSI.
4. Have an appreciation and understanding of physical design and layout and modularization.
5. Be able to use a gate-level layout and synthesis tool (Microwind or equivalent) to analyse the behaviour for some exemplar building blocks.
6. Have an understanding and appreciation of memory devices and circuits and some architectural and system level design via knowledge of interconnects, data flow and synchronization.
Syllabus
Topics may include, but are not limited to:
Introduction to logic design. CMOS physical structure and relation to IC performance limitations
Electrical representation of MOSFETs and gate primitives. SPICE, switch-level and gate-level modelling
Design hierarchy and RTL modelling
Study of some key building blocks; CAD and evaluation
Data flow and routing: interconnect, bus, and clock distribution overview
Memory circuits; devices leading to programmable logic
Teaching methods
| Delivery type | Number | Length hours | Student hours |
| On-line Learning | 8 | 1.00 | 8.00 |
| Independent online learning hours | 32.00 | ||
| Private study hours | 60.00 | ||
| Total Contact hours | 8.00 | ||
| Total hours (100hr per 10 credits) | 100.00 | ||
Private study
Students are expected to use private study time to consolidate the material covered in lectures, to undertake preparatory work for laboratory classes and to prepare for summative assessments.Opportunities for Formative Feedback
Feedback will be mainly provided through the CAD classes and the mini-project report.Methods of assessment
Coursework
| Assessment type | Notes | % of formal assessment |
| Online Assessment | Online Assignment/Test 1 | 7.00 |
| Online Assessment | Online Assignment/Test 2 | 14.00 |
| Online Assessment | Online Assignment/Test 3 | 21.00 |
| Online Assessment | Online Assignment/Test 4 | 28.00 |
| In-course Assessment | CAD Laboratory Assignment | 30.00 |
| Total percentage (Assessment Coursework) | 100.00 | |
.Resits for ELEC and XJEL modules are subject to the School's Resit Policy and the Code of Practice on Assessment (CoPA), which are available on Minerva. Students should be aware that, for some modules, a resit may only be conducted on an internal basis (with tuition) in the next academic session.
Reading list
There is no reading list for this moduleLast updated: 01/02/2021 11:32:42
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