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2020/21 Taught Postgraduate Module Catalogue

ELEC5566M FPGA Design for System-on-Chip

15 creditsClass Size: 130

Module manager: Professor Steven Freear
Email: s.freear@leeds.ac.uk

Taught: 1 Jan to 31 May View Timetable

Year running 2020/21

Pre-requisite qualifications

Students are required to have at least ONE of the following pre-requisites: ELEC3662 or ELEC5681M.

This module is not approved as an Elective

Module summary

The teaching and assessment methods shown below will be kept under review during 2020-21. In particular, if conditions allow for alternative formats of delivery, we may amend the timetable and schedule appropriate classes in addition to (or in place of) the Online Learning Workshops. For Semester 2 (from January 2021), we anticipate that this will be most likely, in which case online teaching will be substituted for traditional face-to-face teaching methods, including lectures and practical classes. ‘Independent online learning’ will involve watching pre-recorded lecture material or screen-casts, engaging in learning activities such as online worked examples or remote/virtual laboratory work, etc. Students will be expected to fully engage with all of these activities. The time commitment for independent online learning, and also the frequency and duration of Online Learning Workshops, are approximate and intended as a guide only. Further details will be confirmed when the module commences.

Objectives

Learning outcomes
On completion of this module students should be able to:

1. The principles of the design of a FPGA systems using Hardware Description Language (Verilog).
2. The use of contemporary EDA design tools: Altera Quartus.
3. Test bench for digital design verification using Mentor Graphics ModelSim.
4. Design of sequential systems using finite state machines.
5. Using fixed point numbering systems to design arithmetic signal processing blocks.
6. Use of bus systems for interlinking complex IP blocks.
7. Parameterisation and re-use for the generation of IP blocks.


Syllabus

Topics may include, but are not limited to:

The principles of the design of a FPGA systems using Hardware Description Language (Verilog)
The use of contemporary EDA design tools: Altera Quartus
Test bench for digital design verification using Mentor Graphics ModelSim
Design of sequential systems using finite state machines
Using fixed point numbering systems to design arithmetic signal processing blocks
Use of bus systems for interlinking complex IP blocks
Parameterisation and re-use for the generation of IP blocks

Teaching methods

Due to COVID-19, teaching and assessment activities are being kept under review - see module enrolment pages for information

Delivery typeNumberLength hoursStudent hours
On-line Learning41.004.00
Independent online learning hours48.00
Private study hours98.00
Total Contact hours4.00
Total hours (100hr per 10 credits)150.00

Private study

Students are expected to read extensively in order to understand and complete the mini projects and the main project. The project will be partly carried out in timetabled classes and partly in the private study time.

Opportunities for Formative Feedback

Students' progress is monitored by assignments and an in-class programming assessment upon which feedback is given.

Methods of assessment

Due to COVID-19, teaching and assessment activities are being kept under review - see module enrolment pages for information


Coursework
Assessment typeNotes% of formal assessment
Online AssessmentOnline Assignment/Test 115.00
Online AssessmentOnline Assignment/Test 220.00
Online AssessmentOnline Assignment/Test 315.00
ProjectComputer-based assignment25.00
VivaOral examination of project25.00
Total percentage (Assessment Coursework)100.00

Resits for ELEC and XJEL modules are subject to the School's Resit Policy and the Code of Practice on Assessment (CoPA), which are available on Minerva. Students should be aware that, for some modules, a resit may only be conducted on an internal basis (with tuition) in the next academic session.

Reading list

There is no reading list for this module

Last updated: 03/12/2020 14:22:50

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