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2020/21 Undergraduate Module Catalogue

ELEC2665 Microprocessors and Programmable Logic

20 creditsClass Size: 160

Module manager: Mr. David Moore

Taught: Semesters 1 & 2 (Sep to Jun) View Timetable

Year running 2020/21

Module replaces

ELEC2660 - Mobile Applications Project

This module is not approved as a discovery module

Module summary

The teaching and assessment methods shown below will be kept under review during 2020-21. In particular, if conditions allow for alternative formats of delivery, we may amend the timetable and schedule appropriate classes in addition to (or in place of) the Online Learning Workshops. For Semester 2 (from January 2021), we anticipate that this will be most likely, in which case online teaching will be substituted for traditional face-to-face teaching methods, including lectures and practical classes. ‘Independent online learning’ will involve watching pre-recorded lecture material or screen-casts, engaging in learning activities such as online worked examples or remote/virtual laboratory work, etc. Students will be expected to fully engage with all of these activities. The time commitment for independent online learning, and also the frequency and duration of Online Learning Workshops, are approximate and intended as a guide only. Further details will be confirmed when the module commences.


This module will extend the learning of digital electronics, following the establishment of the fundamentals in ELEC1620 in year one. The module will teach digital logic implementation from gate level combinational logic, all the way through to machine language and assembly instructions. These topics will be applied as a means of introducing programmable hardware – primarily FPGAs. Students will be taught how to implement digital designs onto programmable hardware, as well as simulate and verify designs before and after implementation. The module will be taught using industry standard tools and a bespoke development kit, giving students insight into various aspects of programmable hardware.

Learning outcomes
On completion of this module students should be able to:

1. Understand and apply engineering principles to the design of elementary logic gates from NAND gates, and the design of arithmetic logic units from logic gates.
2. Understand and apply engineering principles to construct a memory system from flip flops, registers, RAM:.
3. Demonstrate knowledge of how logic gates, units and memory systems can be implemented on programmable hardware.
4. Apply a systems approach to the design of complex digital devices including the combination of the ALU and memory system into a working computer platform.
5. Understand the principles and application of instruction sets for writing programs in low-level assembly language.
6. Demonstrate an understanding of the principles of assemblers.
7. Demonstrate an ability to use simulation tools to verify a design for programmable hardware.
8. Understand the principles of interfacing external peripherals with an FPGA device.


Topics may include, but are not limited to:

Overview of the Hardware Description Language (HDL) used in the course
Implementing logic gates in HDL
Combinational logic: implementation of a binary adder and simple ALU (Arithmetic-Logic Unit) in HDL
Sequential logic: flip-flop gates, registers and memory cells
Design and implementation of a memory hierarchy in HDL
Machine language: introduction of an instruction set in both binary and assembly language
Composition of low-level assembly programs running them on a CPU emulator
Computer architecture: integration of the previous designs into a model computer that executes maching code
Assembler: how an assembler coverts the assembly language files into binary machine code
HDL use in practical applications, specifically Verilog
Comparison of the similarities of Verilog to the bespoke HDL language used in Semester One
Designing digital logic circuits in Quartus which are then programmed onto a custom FPGA platform
Design of complex digital logic circuits, such as carry-lookahead adders and hardware multipliers, implemented in hardware and verified for speed compared to a microcontroller implementation
Introduction to Modelsim as an industry-standard simulation tool, using it to simulate logic designs and confirm their validity before programming onto hardware
Use of external peripherals such as switch inputs, potentiometers, LEDs and Seven Segment Displays to interface with the FPGA via GPIO and on-chip ADCs

Teaching methods

Due to COVID-19, teaching and assessment activities are being kept under review - see module enrolment pages for information

Delivery typeNumberLength hoursStudent hours
On-line Learning161.0016.00
Independent online learning hours64.00
Private study hours120.00
Total Contact hours16.00
Total hours (100hr per 10 credits)200.00

Private study

Students will be expected to complete pre and post lab exercises following each practical session as part of their private study. They will also have access to screencasts which accompany the lab material and will need to be viewed prior to each session, constituting part of their independent online learning.

Opportunities for Formative Feedback

Formative feedback will be given through informal discussion with students during the laboratory sessions. This may be at the request of students or when module staff feel it is necessary as a result of monitoring progress in the classroom.

Methods of assessment

Due to COVID-19, teaching and assessment activities are being kept under review - see module enrolment pages for information

Assessment typeNotes% of formal assessment
Online AssessmentOnline Assignment/Test 115.00
Online AssessmentOnline Assignment/Test 225.00
Online AssessmentOnline Assignment/Test 325.00
Online AssessmentOnline Assignment/Test 435.00
Total percentage (Assessment Coursework)100.00

Resits for ELEC and XJEL modules are subject to the School's Resit Policy and the Code of Practice on Assessment (CoPA), which are available on Minerva. Students should be aware that, for some modules, a resit may only be conducted on an internal basis (with tuition) in the next academic session.

Reading list

There is no reading list for this module

Last updated: 10/08/2020 08:35:35


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