2021/22 Taught Postgraduate Module Catalogue

ELEC5566M FPGA Design for System-on-Chip

15 creditsClass Size: 130

Module manager: Professor Steven Freear
Email: s.freear@leeds.ac.uk

Taught: Semester 2 (Jan to Jun) View Timetable

Year running 2021/22

Pre-requisite qualifications

Students are required to have at least ONE of the following pre-requisites: ELEC2645 or 2665 (for Level 4 undergraduate students) or ELEC5681M (for MSc students).

This module is not approved as an Elective

Module summary

The teaching and assessment methods shown below will be kept under review during 2021-22. In particular, if conditions allow for alternative formats of delivery, we may amend the timetable and schedule appropriate classes in addition to (or in place of) any online activities/sessions. Where learning activities are scheduled to take place on campus, it may be possible and/or necessary for some students to join these sessions remotely. Some of the listed contact hours may also be optional surgeries. Students will be provided with full information about the arrangements for all of these activities by the module staff at the beginning of the teaching semester.‘Independent online learning’ may involve watching pre-recorded lecture material or screen-casts, engaging in learning activities such as online worked examples or mini-projects, etc. Students will be expected to fully engage with all of these activities. The time commitment for independent online learning, and also the frequency and duration of online sessions are approximate and intended as a guide only. Further details will be confirmed when the module commences.Where assessments are shown as Online Time-Limited Assessments, the durations shown are indicative only. The actual time permitted for individual assessments will be confirmed prior to the assessments taking place.

Objectives

This module introduces the design principles of modern FPGA systems using Hardware Description Languages and contemporary, industry-standard design tools.

Learning outcomes
On completion of this module students should be able to:

1. Discuss the detailed principles of FPGA systems and their design using a Hardware Description Language (Verilog).
2. Use contemporary EDA design tools and test-benches for digital design verification.
3. Design sequential systems using finite state machines.
4. Use fixed-point numbering systems to design arithmetic signal processing blocks.
5. Use bus systems for interlinking complex IP blocks.
6. Apply parameterisation and re-use for the generation of IP blocks.

Syllabus

Topics may include, but are not limited to:

The principles of the design of a FPGA systems using Hardware Description Language (Verilog)
The use of contemporary EDA design tools: Altera Quartus
Test bench for digital design verification using Mentor Graphics ModelSim
Design of sequential systems using finite state machines
Using fixed point numbering systems to design arithmetic signal processing blocks
Use of bus systems for interlinking complex IP blocks
Parameterisation and re-use for the generation of IP blocks

Teaching methods

Delivery type	Number	Length hours	Student hours
On-line Learning	18	1.00	18.00
Laboratory	9	2.00	18.00
Independent online learning hours			22.00
Private study hours			92.00
Total Contact hours			36.00
Total hours (100hr per 10 credits)			150.00

Private study

Students are expected to use private study time to consolidate their understanding of course materials, to undertake preparatory work for seminars, workshops, tutorials, examples classes and practical classes, and also to prepare for in-course and summative assessments.

Opportunities for Formative Feedback

Students studying ELEC modules will receive formative feedback in a variety of ways, including the use of self-test quizzes on Minerva, practice questions/worked examples and (where appropriate) through verbal interaction with teaching staff and/or post-graduate demonstrators.

Methods of assessment

Coursework

Assessment type	Notes	% of formal assessment
Assignment	Assignment 1	5.00
Assignment	Assignment 2	30.00
Project	Project 1	50.00
Total percentage (Assessment Coursework)		85.00

Resits for ELEC and XJEL modules are subject to the School's Resit Policy and the Code of Practice on Assessment (CoPA), which are available on Minerva. Students should be aware that, for some modules, a resit may only be conducted on an internal basis (with tuition) in the next academic session.

Exams

Exam type	Exam duration	% of formal assessment
Online Time-Limited assessment	1 hr 00 mins	15.00
Total percentage (Assessment Exams)		15.00

Normally resits will be assessed by the same methodology as the first attempt, unless otherwise stated

Reading list

There is no reading list for this module

Last updated: 22/07/2021 14:42:10

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