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2021/22 Undergraduate Module Catalogue

XJEL3285 Integrated Circuit Design

10 creditsClass Size: 100

Module manager: Dr. Paul Steenson

Taught: Semester 2 (Jan to Jun) View Timetable

Year running 2021/22

This module is not approved as a discovery module

Module summary

The teaching and assessment methods shown below will be kept under review during 2021-22. If it is not possible to deliver traditional teaching methods, such as lectures and practical classes, we may need to substitute alternative (online) formats of delivery and amend the timetable accordingly. ‘Independent online learning’ may involve watching pre-recorded lecture material or screen-casts, engaging in learning activities such as online worked examples or mini-projects, etc. Students will be expected to fully engage with all of these activities. The time commitment for independent online learning, and also the frequency and duration of online sessions are approximate and intended as a guide only. Further details will be confirmed when the module commences.Where assessments are shown as Online Time-Limited Assessments, the durations shown are indicative only. The actual time permitted for individual assessments will be confirmed prior to the assessments taking place.


To provide students with a knowledge, understanding and hands-on experience of VLSI design, primarily from a logic-circuit perspective, but including an introduction to contemporary VLSI chips, such as CPLDs and FPGAs, and the associated hierarchical and top-down (HDL) design methodologies leading to increasing complexity.

Learning outcomes
On completion of this module students should be able to:

1. Explain the principles of complex VLSI design and systems.
2. Describe combinational and sequential logic representations and their circuit implementation.
3. Explain the electrical properties of silicon logic, MOSFET, gate-level and switch-level elements of VLSI systems.
4. Use mathematical models to understand and implement design decisions and trade-offs.
5. Apply the principles of physical design, layout and modularisation to a VSLI design problems.
6. Use a CAD tool to analyse the behaviour of complex VLSI system blocks.
7. Explain the operation of memory devices and circuits, including the principles of architectural and system level design using interconnects, data flow and synchronisation.


Topics may include, but are not limited to:

Introduction to logic design. CMOS physical structure and relation to IC performance limitations
Electrical representation of MOSFETs and gate primitives. SPICE, switch-level and gate-level modelling
Design hierarchy and RTL modelling
Study of some key building blocks; CAD and evaluation
Data flow and routing: interconnect, bus, and clock distribution overview
Memory circuits; devices leading to programmable logic

Teaching methods

Delivery typeNumberLength hoursStudent hours
Examples Class61.006.00
Private study hours62.00
Total Contact hours38.00
Total hours (100hr per 10 credits)100.00

Private study

Students are expected to use private study time to consolidate their understanding of course materials, to undertake preparatory work for seminars, workshops, tutorials, examples classes and practical classes, and also to prepare for in-course and summative assessments.

Opportunities for Formative Feedback

Students studying ELEC modules will receive formative feedback in a variety of ways, including the use of self-test quizzes on Minerva, practice questions/worked examples and (where appropriate) through verbal interaction with teaching staff and/or post-graduate demonstrators.

Methods of assessment

Assessment typeNotes% of formal assessment
AssignmentAssignment 140.00
Total percentage (Assessment Coursework)40.00

Resits for ELEC and XJEL modules are subject to the School's Resit Policy and the Code of Practice on Assessment (CoPA), which are available on Minerva. Students should be aware that, for some modules, a resit may only be conducted on an internal basis (with tuition) in the next academic session.

Exam typeExam duration% of formal assessment
Online Time-Limited assessment2 hr 00 mins30.00
Online Time-Limited assessment2 hr 00 mins30.00
Total percentage (Assessment Exams)60.00

Normally resits will be assessed by the same methodology as the first attempt, unless otherwise stated

Reading list

There is no reading list for this module

Last updated: 29/06/2021 16:47:30


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