2023/24 Taught Postgraduate Module Catalogue
ELEC5566M FPGA Design for System-on-Chip
15 creditsClass Size: 160
Module manager: Professor Steven Freear
Taught: Semester 2 (Jan to Jun) View Timetable
Year running 2023/24
Pre-requisite qualificationsStudents are required to have at least ONE of the following pre-requisites: ELEC2645 or 2665 (for Level 4 undergraduate students) or ELEC5681M (for MSc students).
This module is not approved as an Elective
ObjectivesThis module introduces the design principles of modern FPGA systems using Hardware Description Languages and contemporary, industry-standard design tools.
On completion of this module students should be able to:
1. Discuss the detailed principles of FPGA systems and their design using a Hardware Description Language (Verilog).
2. Use contemporary EDA design tools and test-benches for digital design verification.
3. Design sequential systems using finite state machines.
4. Use fixed-point numbering systems to design arithmetic signal processing blocks.
5. Use bus systems for interlinking complex IP blocks.
6. Apply parameterisation and re-use for the generation of IP blocks.
Topics may include, but are not limited to:
The principles of the design of a FPGA systems using Hardware Description Language (Verilog)
The use of contemporary EDA design tools: Altera Quartus
Test bench for digital design verification using Mentor Graphics ModelSim
Design of sequential systems using finite state machines
Using fixed point numbering systems to design arithmetic signal processing blocks
Use of bus systems for interlinking complex IP blocks
Parameterisation and re-use for the generation of IP blocks
|Delivery type||Number||Length hours||Student hours|
|Private study hours||119.00|
|Total Contact hours||31.00|
|Total hours (100hr per 10 credits)||150.00|
Private studyStudents are expected to use private study time to consolidate their understanding of course materials, to undertake preparatory work for seminars, workshops, tutorials, examples classes and practical classes, and also to prepare for in-course and summative assessments.
Opportunities for Formative FeedbackStudents studying ELEC modules will receive formative feedback in a variety of ways, including the use of self-test quizzes on Minerva, practice questions/worked examples and (where appropriate) through verbal interaction with teaching staff and/or post-graduate demonstrators.
Methods of assessment
|Assessment type||Notes||% of formal assessment|
|In-course Assessment||Programming Assignment||30.00|
|In-course Assessment||Mini-Group Project||40.00|
|Total percentage (Assessment Coursework)||70.00|
Resits for ELEC and XJEL modules are subject to the School's Resit Policy and the Code of Practice on Assessment (CoPA), which are available on Minerva. Students should be aware that, for some modules, a resit may only be conducted on an internal basis (with tuition) in the next academic session.
|Exam type||Exam duration||% of formal assessment|
|Unseen Practical exam (S2)||1 hr 00 mins||0.00|
|Standard exam (closed essays, MCQs etc)||3 hr 00 mins||30.00|
|Total percentage (Assessment Exams)||30.00|
Normally resits will be assessed by the same methodology as the first attempt, unless otherwise stated
Reading listThere is no reading list for this module
Last updated: 27/10/2023
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